Model-Based Test Design in SysML for System Requirements Verification and Validation

In complex system development, testing often remains disconnected from requirements and architecture models — leading to traceability issues and unclear validation logic. In this talk, Elif Ugur presents a novel method to bridge that gap using Systems Modeling Language (SysML)-based test case design. The approach shows how test steps, test data, and expected results can be modeled directly within SysML diagrams to improve consistency and support system-level verification. Based on a real-world use case involving the digital twin of a high-voltage cable system, this session demonstrates how structured, Model-Based Test Design (MBTD) enhances both clarity and test coverage.

Value for the audience:
Attendees will learn how to integrate test design into SysML using existing diagrams, enabling better alignment between requirements and testing. The session offers practical insights into improving traceability, minimizing miscommunication, and making Model-Based Systems Engieering (MBSE) more test-inclusive.

Talk language: English
Level: Scientific
Target group: systems engineers, testers, quality-focused development teams

Company:
Fraunhofer IEM, Fachhochschule Südwestfalen

M. Sc. Elif Ugur